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Macros</h2></td></tr>
<tr class="memitem:ga985ef58212940c666ada245d3e83a17d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga985ef58212940c666ada245d3e83a17d">XIICPS_HW_H</a></td></tr>
<tr class="memdesc:ga985ef58212940c666ada245d3e83a17d"><td class="mdescLeft">&#160;</td><td class="mdescRight">by using protection macros  <a href="group__iicps__api.html#ga985ef58212940c666ada245d3e83a17d">More...</a><br/></td></tr>
<tr class="separator:ga985ef58212940c666ada245d3e83a17d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabcc20fce80c1e8dff27be4e584c2cc27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#gabcc20fce80c1e8dff27be4e584c2cc27">XIicPs_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XIicPs_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gabcc20fce80c1e8dff27be4e584c2cc27"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads an IIC register.  <a href="group__iicps__api.html#gabcc20fce80c1e8dff27be4e584c2cc27">More...</a><br/></td></tr>
<tr class="separator:gabcc20fce80c1e8dff27be4e584c2cc27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0bde6894589023ea8248a9d9cdc73c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#gaa0bde6894589023ea8248a9d9cdc73c5">XIicPs_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:gaa0bde6894589023ea8248a9d9cdc73c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes an IIC register.  <a href="group__iicps__api.html#gaa0bde6894589023ea8248a9d9cdc73c5">More...</a><br/></td></tr>
<tr class="separator:gaa0bde6894589023ea8248a9d9cdc73c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8f0f78d7389924d17d2b7b49f622cf1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#gab8f0f78d7389924d17d2b7b49f622cf1">XIicPs_ReadIER</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group__iicps__api.html#gabcc20fce80c1e8dff27be4e584c2cc27">XIicPs_ReadReg</a>((BaseAddress),  <a class="el" href="group__iicps__api.html#ga471cbaf2444941e33de173ea5e5c7f03">XIICPS_IER_OFFSET</a>)</td></tr>
<tr class="memdesc:gab8f0f78d7389924d17d2b7b49f622cf1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the interrupt enable register.  <a href="group__iicps__api.html#gab8f0f78d7389924d17d2b7b49f622cf1">More...</a><br/></td></tr>
<tr class="separator:gab8f0f78d7389924d17d2b7b49f622cf1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7a3f4b57fe275f426ac9b771b187b23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#gaf7a3f4b57fe275f426ac9b771b187b23">XIicPs_EnableInterrupts</a>(BaseAddress, IntrMask)&#160;&#160;&#160;<a class="el" href="group__iicps__api.html#gaa0bde6894589023ea8248a9d9cdc73c5">XIicPs_WriteReg</a>((BaseAddress), <a class="el" href="group__iicps__api.html#ga471cbaf2444941e33de173ea5e5c7f03">XIICPS_IER_OFFSET</a>, (IntrMask))</td></tr>
<tr class="memdesc:gaf7a3f4b57fe275f426ac9b771b187b23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes to the interrupt enable register.  <a href="group__iicps__api.html#gaf7a3f4b57fe275f426ac9b771b187b23">More...</a><br/></td></tr>
<tr class="separator:gaf7a3f4b57fe275f426ac9b771b187b23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90efda2a784d4b972f1835b0ba81cde1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga90efda2a784d4b972f1835b0ba81cde1">XIicPs_DisableAllInterrupts</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga90efda2a784d4b972f1835b0ba81cde1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables all interrupts.  <a href="group__iicps__api.html#ga90efda2a784d4b972f1835b0ba81cde1">More...</a><br/></td></tr>
<tr class="separator:ga90efda2a784d4b972f1835b0ba81cde1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a21536b3361fa36f00745a3e653fbbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga6a21536b3361fa36f00745a3e653fbbd">XIicPs_DisableInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:ga6a21536b3361fa36f00745a3e653fbbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables selected interrupts.  <a href="group__iicps__api.html#ga6a21536b3361fa36f00745a3e653fbbd">More...</a><br/></td></tr>
<tr class="separator:ga6a21536b3361fa36f00745a3e653fbbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the IIC. </p>
</div></td></tr>
<tr class="memitem:ga0c96ab97015c857822df599608ba9c10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga0c96ab97015c857822df599608ba9c10">XIICPS_CR_OFFSET</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga0c96ab97015c857822df599608ba9c10"><td class="mdescLeft">&#160;</td><td class="mdescRight">32-bit Control  <a href="group__iicps__api.html#ga0c96ab97015c857822df599608ba9c10">More...</a><br/></td></tr>
<tr class="separator:ga0c96ab97015c857822df599608ba9c10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12b4d0ee4dce6172ba78a0dec5666a72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga12b4d0ee4dce6172ba78a0dec5666a72">XIICPS_SR_OFFSET</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga12b4d0ee4dce6172ba78a0dec5666a72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status.  <a href="group__iicps__api.html#ga12b4d0ee4dce6172ba78a0dec5666a72">More...</a><br/></td></tr>
<tr class="separator:ga12b4d0ee4dce6172ba78a0dec5666a72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d97551edd7013b07093cac16dbe80f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga3d97551edd7013b07093cac16dbe80f1">XIICPS_ADDR_OFFSET</a>&#160;&#160;&#160;0x08U</td></tr>
<tr class="memdesc:ga3d97551edd7013b07093cac16dbe80f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC Address.  <a href="group__iicps__api.html#ga3d97551edd7013b07093cac16dbe80f1">More...</a><br/></td></tr>
<tr class="separator:ga3d97551edd7013b07093cac16dbe80f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9101ca416d8b9e303b4a65c4840a1d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#gac9101ca416d8b9e303b4a65c4840a1d5">XIICPS_DATA_OFFSET</a>&#160;&#160;&#160;0x0CU</td></tr>
<tr class="memdesc:gac9101ca416d8b9e303b4a65c4840a1d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">IIC FIFO Data.  <a href="group__iicps__api.html#gac9101ca416d8b9e303b4a65c4840a1d5">More...</a><br/></td></tr>
<tr class="separator:gac9101ca416d8b9e303b4a65c4840a1d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ec604e5ed330606d24a082484e905f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga9ec604e5ed330606d24a082484e905f0">XIICPS_ISR_OFFSET</a>&#160;&#160;&#160;0x10U</td></tr>
<tr class="memdesc:ga9ec604e5ed330606d24a082484e905f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status.  <a href="group__iicps__api.html#ga9ec604e5ed330606d24a082484e905f0">More...</a><br/></td></tr>
<tr class="separator:ga9ec604e5ed330606d24a082484e905f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2afdc061285f0155f3fbbf322beae54f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga2afdc061285f0155f3fbbf322beae54f">XIICPS_TRANS_SIZE_OFFSET</a>&#160;&#160;&#160;0x14U</td></tr>
<tr class="memdesc:ga2afdc061285f0155f3fbbf322beae54f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Size.  <a href="group__iicps__api.html#ga2afdc061285f0155f3fbbf322beae54f">More...</a><br/></td></tr>
<tr class="separator:ga2afdc061285f0155f3fbbf322beae54f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3750481db8ebadadea48985f0abcb755"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga3750481db8ebadadea48985f0abcb755">XIICPS_SLV_PAUSE_OFFSET</a>&#160;&#160;&#160;0x18U</td></tr>
<tr class="memdesc:ga3750481db8ebadadea48985f0abcb755"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave monitor pause.  <a href="group__iicps__api.html#ga3750481db8ebadadea48985f0abcb755">More...</a><br/></td></tr>
<tr class="separator:ga3750481db8ebadadea48985f0abcb755"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61f5015241d07352f5cad00c589ec4e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga61f5015241d07352f5cad00c589ec4e0">XIICPS_TIME_OUT_OFFSET</a>&#160;&#160;&#160;0x1CU</td></tr>
<tr class="memdesc:ga61f5015241d07352f5cad00c589ec4e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time Out.  <a href="group__iicps__api.html#ga61f5015241d07352f5cad00c589ec4e0">More...</a><br/></td></tr>
<tr class="separator:ga61f5015241d07352f5cad00c589ec4e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0668ec3389dd427fecfca4d1b9d2f0c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga0668ec3389dd427fecfca4d1b9d2f0c4">XIICPS_IMR_OFFSET</a>&#160;&#160;&#160;0x20U</td></tr>
<tr class="memdesc:ga0668ec3389dd427fecfca4d1b9d2f0c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enabled Mask.  <a href="group__iicps__api.html#ga0668ec3389dd427fecfca4d1b9d2f0c4">More...</a><br/></td></tr>
<tr class="separator:ga0668ec3389dd427fecfca4d1b9d2f0c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga471cbaf2444941e33de173ea5e5c7f03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga471cbaf2444941e33de173ea5e5c7f03">XIICPS_IER_OFFSET</a>&#160;&#160;&#160;0x24U</td></tr>
<tr class="memdesc:ga471cbaf2444941e33de173ea5e5c7f03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable.  <a href="group__iicps__api.html#ga471cbaf2444941e33de173ea5e5c7f03">More...</a><br/></td></tr>
<tr class="separator:ga471cbaf2444941e33de173ea5e5c7f03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac95b4e2bd04257b322e5bf66f956bdf3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#gac95b4e2bd04257b322e5bf66f956bdf3">XIICPS_IDR_OFFSET</a>&#160;&#160;&#160;0x28U</td></tr>
<tr class="memdesc:gac95b4e2bd04257b322e5bf66f956bdf3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Disable.  <a href="group__iicps__api.html#gac95b4e2bd04257b322e5bf66f956bdf3">More...</a><br/></td></tr>
<tr class="separator:gac95b4e2bd04257b322e5bf66f956bdf3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">IIC Interrupt Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b>IIC Interrupt Status Register</b></p>
<p>This register holds the interrupt status flags for the IIC controller. Some of the flags are level triggered</p>
<ul>
<li>i.e. are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set one the interrupt condition occurs then remain set until they are cleared by software. The interrupts are cleared by writing a one to the interrupt bit position in the Interrupt Status Register. Read/Write.</li>
</ul>
<p><b>IIC Interrupt Enable Register</b></p>
<p>This register is used to enable interrupt sources for the IIC controller. Writing a '1' to a bit in this register clears the corresponding bit in the IIC Interrupt Mask register. Write only.</p>
<p><b>IIC Interrupt Disable Register </b></p>
<p>This register is used to disable interrupt sources for the IIC controller. Writing a '1' to a bit in this register sets the corresponding bit in the IIC Interrupt Mask register. Write only.</p>
<p><b>IIC Interrupt Mask Register</b></p>
<p>This register shows the enabled/disabled status of each IIC controller interrupt source. A bit set to 1 will ignore the corresponding interrupt in the status register. A bit set to 0 means the interrupt is enabled. All mask bits are set and all interrupts are disabled after reset. Read only.</p>
<p>All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Interrupt Status Register </p>
</div></td></tr>
<tr class="memitem:ga88441aea66e1ef8f1fd211756b1d1630"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga88441aea66e1ef8f1fd211756b1d1630">XIICPS_IXR_ARB_LOST_MASK</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga88441aea66e1ef8f1fd211756b1d1630"><td class="mdescLeft">&#160;</td><td class="mdescRight">Arbitration Lost Interrupt mask.  <a href="group__iicps__api.html#ga88441aea66e1ef8f1fd211756b1d1630">More...</a><br/></td></tr>
<tr class="separator:ga88441aea66e1ef8f1fd211756b1d1630"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b92f85baedcc73892a141f80afe3462"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga6b92f85baedcc73892a141f80afe3462">XIICPS_IXR_RX_UNF_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga6b92f85baedcc73892a141f80afe3462"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO Receive Underflow Interrupt mask.  <a href="group__iicps__api.html#ga6b92f85baedcc73892a141f80afe3462">More...</a><br/></td></tr>
<tr class="separator:ga6b92f85baedcc73892a141f80afe3462"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2473caf4558fac9af1bd071a022e3cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#gad2473caf4558fac9af1bd071a022e3cf">XIICPS_IXR_TX_OVR_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gad2473caf4558fac9af1bd071a022e3cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Overflow Interrupt mask.  <a href="group__iicps__api.html#gad2473caf4558fac9af1bd071a022e3cf">More...</a><br/></td></tr>
<tr class="separator:gad2473caf4558fac9af1bd071a022e3cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f69893ddec793ff77b61deb51665aa5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga1f69893ddec793ff77b61deb51665aa5">XIICPS_IXR_RX_OVR_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga1f69893ddec793ff77b61deb51665aa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Overflow Interrupt mask.  <a href="group__iicps__api.html#ga1f69893ddec793ff77b61deb51665aa5">More...</a><br/></td></tr>
<tr class="separator:ga1f69893ddec793ff77b61deb51665aa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c873e7df9f7a05e458b0d7e9b50faa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga5c873e7df9f7a05e458b0d7e9b50faa9">XIICPS_IXR_SLV_RDY_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga5c873e7df9f7a05e458b0d7e9b50faa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Monitored Slave Ready Interrupt mask.  <a href="group__iicps__api.html#ga5c873e7df9f7a05e458b0d7e9b50faa9">More...</a><br/></td></tr>
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<tr class="memitem:ga6df84833528a63b5f5fb07a7d1743c91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga6df84833528a63b5f5fb07a7d1743c91">XIICPS_IXR_TO_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga6df84833528a63b5f5fb07a7d1743c91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Time Out Interrupt mask.  <a href="group__iicps__api.html#ga6df84833528a63b5f5fb07a7d1743c91">More...</a><br/></td></tr>
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<tr class="memitem:ga74650276000c8cc48cce610b8c6d2140"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga74650276000c8cc48cce610b8c6d2140">XIICPS_IXR_NACK_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga74650276000c8cc48cce610b8c6d2140"><td class="mdescLeft">&#160;</td><td class="mdescRight">NACK Interrupt mask.  <a href="group__iicps__api.html#ga74650276000c8cc48cce610b8c6d2140">More...</a><br/></td></tr>
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<tr class="memitem:gaa4e9c302ebb54b53aa67ec6c9f4616a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#gaa4e9c302ebb54b53aa67ec6c9f4616a3">XIICPS_IXR_DATA_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaa4e9c302ebb54b53aa67ec6c9f4616a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interrupt mask.  <a href="group__iicps__api.html#gaa4e9c302ebb54b53aa67ec6c9f4616a3">More...</a><br/></td></tr>
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<tr class="memitem:ga56fefd834bba9cc03c0a84bd2a3e099a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga56fefd834bba9cc03c0a84bd2a3e099a">XIICPS_IXR_COMP_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga56fefd834bba9cc03c0a84bd2a3e099a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Complete Interrupt mask.  <a href="group__iicps__api.html#ga56fefd834bba9cc03c0a84bd2a3e099a">More...</a><br/></td></tr>
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<tr class="memitem:ga98fd97807996f571433d9235dc0b0ca4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga98fd97807996f571433d9235dc0b0ca4">XIICPS_IXR_DEFAULT_MASK</a>&#160;&#160;&#160;0x000002FFU</td></tr>
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<tr class="memitem:ga8e324637da3483d518d499b7257c7631"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__iicps__api.html#ga8e324637da3483d518d499b7257c7631">XIICPS_IXR_ALL_INTR_MASK</a>&#160;&#160;&#160;0x000002FFU</td></tr>
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